A fast array architecture for block matching algorithm
Junhyun Baek, Seung-Hyun Nam, Moonkey Lee, Chuldong Oh, Kisoo Hwang · 2002
The block-matching motion estimation is the most popular method for motion-compensated coding of image sequence. Based on two dimensional systolic array, VLSI architecture for an implementation of full-search block matching algorithm is described. The proposed architecture has the following advantages: (1) it allows serial data inputs to save pin counts but performs parallel processing. (2) It is flexible in adaptation to the dimensional change of search window with simple control logic. (3) It has no idle time during the operation. (4) It can operate in real time for videoconference application and EDTV application. (5) It is modular and regular in design, and thus suitable for VLSI implementation.>