Minimizing power consumption in scan testing: pattern generation and DFT techniques
Kenneth M. Butler, J. Saxena, Ankit Jain, T. Fryars, J. Lewis, G. Hetherington · 2005
It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.