A combined 16-bit binary and dual Galois field multiplier
Javier Espinosa García, Michael Schulte · 2003
Galois field arithmetic is commonly used in Reed-Solomon encoding and decoding. This paper presents the design of a combined 16-bit binary and dual Galois field (GF) multiplier. This multiplier is capable of performing either a 16-bit two's complement or unsigned multiplication, or two independent 8-bit GF(2/sup 8/) multiplications in SIMD fashion. The combined multiplier is designed by modifying a conventional binary tree multiplier. It uses a novel wiring methodology to provide two simultaneous GF(2/sup 8/) multiplies with a minor impact on area and delay. Two alternatives for the multiplier design are presented. Area and delay estimates indicate that compared to a conventional binary tree multiplier, the combined multiplier has roughly 6% more delay and 23% more area.