A 16 MB cache DRAM LSI with internal 35.8 GB/s memory bandwidth for simultaneous read and write operation
Masato Nakayama, Hideki Sakakibara, M. Kusunoki, K. Kurita, Y. Yokoyama, S. Miyaoka, Junichi Koike, N. Tamba, Tsukasa Kobayashi, M. Kume, Hideo Sawamoto, A. Kawata, H. Tanaka, Y. Takada, Masataka Yamamoto, Masayoshi Yagyu, Y. Tsuchiya, H. Yoshida, N. Kitamura, K. Yamaguchi · 2002
With continuous scaling of process technology, embedded DRAM technology becomes promising for high performance cache memory systems because of its potential of large memory capacity and high bandwidth. Although several papers reported, none of them has enough memory bandwidth or capacity for high-end computer applications. This 16 MB cache DRAM LSI chip with internal 35.8 GB/s memory bandwidth and 9.0 ns DRAM random access latency uses merged logic DRAM process technology that combines leading-edge DRAM devices equivalent to that of 256 Mb conventional DRAM with high-speed 0.2 /spl mu/m CMOS logic.