3D Architecture Exploration for Multimedia Applications
Winston Siauw · Research Repository (Delft University of Technology) · 2010
Three-Dimensional (3D) silicon integration is an emerging technology that vertically stacks multiple silicon circuit layers. It enables a single chip to be divided over multiple layers, which are stacked on top of each other. A literature study is performed for this thesis, which presents the basic manufacturing techniques for this emerging technology. Furthermore, the constraints and properties of the inter-layer interconnect (Through Silicon Via (TSV)) are investigated, and the architectural potentials of 3D silicon integration are explored for memory-on-memory, logic-on-logic, memoryon-logic, and a 3D Network-On-Chip (NOC). Compared to a planar chip, 3D integration provides five key advantages: (1) wider and denser on-chip interconnects / busses, (2) wire length reduction (latency reduction), (3) lower power consumption, (4) the potential to use heterogeneous technologies, and (5) footprint reduction. Moreover, practical work is performed for this thesis, which evaluates a novel 3D scheme. The scheme stacks two (or more) 2D processors on top of each other, where all the Functional Units (FUs) are shared between all the processors. Thus, a processor can execute instructions on all the unutilized FUs of all the (remaining) processors. The free FUs on other processors can be utilized for fault detection or for performance improvement. Experimental results show that on average 52% of the executed instructions can be protected, or a speedup of on average 7% can be achieved. Both schemes are beneficial because no extra dedicated FUs are needed and fault detection and higher performance are achieved at low cost (only additional control logic and TSVs). This is because all the FUs from the processors are shared between them.