Exploiting run-time reconfigurable hardware in the development of automatic fingerprint-based personal recognition applications
Francisco Fons, Mariano Fons · InTech eBooks · 2011
Recent Application in Biometrics 240 complexity, the processing power and the costs of the physical systems where to implement those applications.This works focuses on the search of the proper system architecture able to face those demanding constraints for the application: a high computational power needed to achieve reliable recognition performances in terms of False Acceptance and False Rejection rates (FAR/FRR), a high security level in order to stand any kind of external attacks (cryptographic systems), real-time performance, and low cost.A novel approach of embedded system based on programmable logic devices such as field programmable gate arrays (FPGA), hardware-software co-design techniques, and the exploitation of run-time reconfigurable hardware is proven to successfully address the above requirements.This chapter is split in nine sections and in each of the sections specific research topics are addressed.Section 2 provides a general overview of the proposed application to be dealt in this work: the development of an Automatic Fingerprint-based Authentication System (AFAS) in charge of verifying the identity of any individual based on the analysis of that distinctive information available in fingerprints.A description of the proposed personal recognition algorithm to be used as reference in this work and to be implemented under different processing platforms is presented.The accuracy performance achieved by the suggested algorithm when evaluated on a large database of fingerprints is addressed in Section 3. One public database composed of up to 800 fingerprint images corresponding to 100 different individuals is used for evaluation purposes.Impostor and Genuine distributions, as well as performance indicators such as FAR, FRR or EER (Equal Error Rate) are given in order to objectively compare the reached performance with the performance of other published algorithms evaluated with the same open database.After presenting the accuracy performance exhibited by the proposed recognition algorithm, Section 4 aims at defining the proper system requirements for the physical platform in charge of the authentication process.The main goal is to find a flexible and high-performance processing platform able to deploy the biometric security in a wide range of daily use applications at low cost, therefore an embedded system architecture is suggested.Two different implementations of the same recognition algorithm are carried out in this work.The first implementation, covered in Section 5, is based on purely software-based solutions.One high performance computing (HPC) platform under Windows operating system and three different embedded system platforms based on low-cost and mid-performance microprocessors are evaluated.The strengths and weaknesses of each of the architectures are pointed out, and based on that information, a different embedded system architecture is suggested in Section 6 to overcome the main limitations exhibited by the previous systems.An embedded system architecture based on a general-purpose microprocessor acting as application core processor, and a programmable and run-time reconfigurable logic region where to instantiate -multiplexed in time and under demand-application-specific hardware coprocessors in charge of the execution of those time-intensive tasks is proposed as alternative solution.Both the microprocessor unit and the hardware accelerators, together with memory blocks and other peripherals are all embedded under a System-on-Programmable-Chip (SoPC) device to provide a highly integrated and more reliable solution.The second implementation of the AFAS application under the proposed embedded system architecture is covered in Section 7. The performance achieved in this new scenario is compared against that of previous scenarios.An outstanding improvement in performance is achieved at a reasonable cost.The work ends with some concluding www.intechopen.