A Streaming Multi-Threaded Model
Eylon Caspi, André M. DeHon, John Wawrzynek · 2001
We present SCORE (Stream Computations Organized for Reconfigurable Execution), a multi-threaded model that relies on streams to expose thread parallelism and to enable e#cient scheduling, low-overhead communication, and scalability. We present work to-date on SCORE for scalable reconfigurable logic, as well as implementation ideas for SCORE for processor architectures. We demonstrate that streams can be exposed as a clean architectural feature that supports forward compatibility to larger, more parallel hardware. 1. OVERVIEW For the past several decades, the predominant architectural abstraction for programmable computation systems has been the instruction set architecture (ISA). An ISA defines an instruction set and semantics for executing it. A key benefit of the ISA model is that those semantics decouple software from hardware development. A piece of software, written and compiled once, is guaranteed to run on any ISA-compatible device. This guarantee allows hardware to evolve...