Improved SVD systolic array and implementation on FPGA
A. Ahmedsaid, Abbes Amira, Ahmed Bouridane · 2004
This paper presents an efficient systolic array for the computation of the Singular Value Decomposition (SVD). The proposed architecture is three times more efficient and faster than the Brent, Luk, Van Loan (BLV) SVD systolic array. The architecture has been implemented efficiently on FPGA using a high level language for hardware design "Handel-C".