Max-Log-MAP Mapping on an FPFA
P.M. Heysters, Lodewijk T. Smit, Gerardus Johannes Maria Smit, Paul Havinga · University of Twente Research Information · 2002
Computational-intensive parts of algorithms often execute energy-inefficient on general-purpose processors. Reconfigurable hardware could improve the energy efficiency while maintaining a sufficient level of flexibility. In a case study, the computational-intensive Max-log-MAP algorithm of Turbo decoding is mapped on the Field Programmable Function Array (FPFA). The FPFA is an architecture for a dynamically reconfigurable device that consists of a matrix of reconfigurable processor tiles.