Exploiting visa for higher concurrency in safe real-time systems
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller · 2004
Worst-case execution times (WCET) of tasks are essential for safe scheduling in hard real-time systems. However, contemporary processors exceed the capabilities of static worst-case timing analysis tools. The Virtual Simple Architecture (VISA) framework shifts the burden of bounding the WCET of tasks, in part, to hardware. A VISA is the pipeline timing specification of a hypothetical simple processor. WCET is derived for a task assuming the VISA. Nonetheless, at run-time, the task is executed speculatively on an unsafe complex processor, and its progress is continuously gauged. If continued safe progress appears to be in jeopardy, the complex processor is reconfigured to a simple mode of operation that directly implements the VISA, thereby explicitly bounding the task's overall execution time by the WCET.