Row-redundancy scheme for high-density flash memory
M. Mihara, T. Nakayama, M. Ohkawa, S. Kawai, Y. Miyawaki, Y. Terada, Makoto Ohi, Hiroshi Onoda, N. Ajika, M. Hatanaka, Hirokazu Miyoshi, Tatsuhiko Yoshihara · 2002
Flash memory is recognized as one of the key devices of personal digital assistant and other portable equipment. Rapid expansion of the market is expected because it is estimated that the cost of flash memory will eventually be lower than that of DRAM. However, to achieve low cost, a highly efficient redundancy scheme must be implemented for the chip. Although the same column redundancy scheme used in DRAM and SRAM can be applied to flash memory, conventional row redundancy in which defective word lines are replaced by spare word lines is not suitable. In flash memory, all memory cells in the erase block must be programmed before the erase pulse is applied to the memory array to avoid over-erasure. If the replaced word line is shorted to the adjacent word line, memory cells on the defective word line cannot be programmed even if the replaced word line is selected because the word line is grounded through the adjacent word line.>