A 300 MHz dual port graphics RAM using port swap architecture
Y. Nakase, Kazuki Mashiko, T. Tokuda · 2002
Graphics controllers are required to implement more functions such as 3D-RAM control and NTSC encoder. The color palette SRAM has been a great area eater in the controllers because of its dual port organization. Its memory cell size has been more than 50% larger than those of single port SRAMs. Single bit-line read/write architectures are effective for area reduction. However, there are problems of operation reliability or slow speed. The port swap architecture realizes a small memory cell size without the problems. The cell size is reduced more than 24%. The color palette with this architecture is fabricated in a 0.5 /spl mu/m CMOS process technology and operates up to 300 MHz. This speed is enough to support the practical highest resolution monitors in the world.