A 54 Mbps (3,6)-regular FPGA LDPC decoder
Tong Zhang, Keshab K. Parhi · 2003
Applying a joint code and decoder design methodology, we develop a high-speed (3, k)-regular LDPC code partly parallel decoder architecture, based on which a 9216-bit, rate-1/2 (3,6)-regular LDPC code decoder is implemented on an Xilinx FPGA device. When performing maximum 18 iterations for each code block decoding, this partly parallel decoder supports a maximum symbol throughput of 54 Mbps and achieves BER 10/sup -6/ at 2 dB over an AWGN channel.