The ideal SoC memory: 1T-SRAM/sup TM/
W.-B. Leung, Fu-Chieh Hsu, Matthew Jones · 2002
The advances of process technology makes system-on-a-chip a reality and present major challenge to IC design. Integration of memory in SoC is further complicated by the incompatibility of memory process technology to the logic process. The simplicity of 1T-SRAM cell facilitates its easy porting to most processes. This helps alleviate the problem of process incompatibility. The simplicity of the cell structure also makes it extremely scalable and cost effective. The challenges of using this cell to satisfy the requirement of embedded SRAM are high-frequency operation, short latency, transparent refresh and soft-error rate. The use of multi-bank architecture and the leverage of multi-layer metal interconnect available in logic processes, allow these challenges to be met readily.