A programmable interpolation and decimation structure for constant-rate high-speed ΣΔ-converters
Thomas Magesacher, L. Gazsi · 2003
An area efficient programmable filter structure for sampling rate conversion by an arbitrary ratio for high speed constant-rate /spl Sigma//spl Delta/-converters is proposed. Utilizing cascaded lattice wave digital filters in a carry-save architecture with canonic signed-digit coefficients, oversampling ratio and filter characteristic can be programmed using minimum coefficient length. For the implemented 5/sup th/ order Bessel and 4/sup th/ order Butterworth filters used in a variable symbol rate digital subscriber line (DSL) system, the passband edge frequencies can be tuned from 20 kHz to 200 kHz in 2.6 kHz steps with only 25 bits per filter which cannot be achieved with any other IIR or FIR structure. Implementation results of the filters fabricated in a 0.35 /spl mu/m CMOS process using a standard static logic cell library are presented.