An 8MIPS CMOS digital signal processor
Jef van Meerbergen, F.P.J.M. Welten, Frank van Wijk, Jan Stoter, Jos Huisken, A. Delaruelle, K. van Eerdewijk, Josef Schmid, Joern Wittek · 1986
A 2μm digital signal processor with a 125ns instruction cycle will be described. It contains two 16b data buses, executes a 40b orthogonal instruction set and supports up to six concurrent arithmetic and data-move operations in each instruction.