A high bandwidth superscalar microprocessor for multimedia applications
F.M. Raam, R. Agarwal, K. Malik, Howard A. Landman, Haruyuki Tago, T. Teruyama, Tadashi Sakamoto, T. Yoshida, S. Yoshioka, Y. Fujimoto, Toshiaki Kobayashi, T. Hiroi, M. Oka, Akio Ohba, M. Suzuoki, T. Yutaka, Yasuyuki Yamamoto · 2003
This 250 MHz 2-way superscalar MIPS-compatible embedded microprocessor is targeted for use in high-end consumer electronics, game, and network markets. The microprocessor features a high-bandwidth (2.0 GB/s peak) 128 b external bus. Internal datapaths and load/store paths to and from the caches are also 128 b wide. Numerous functional enhancements are incorporated, including a 128 b SIMD instruction set for multimedia support, an integrated scratchpad RAM (SPRAM), and a comprehensive set of debug and performance counting facilities.