Design and implementation of a fast and compact residue-based semi-custom VLSI arithmetic chip
Ahmad Hiasat, H.S. Abdel-Aty-Zohdy · 2002
Design and implementation of a residue-based adder/subtractor/multiplier arithmetic TinyChip for the moduli set (2/sup n/-1,2/sup n/,2/sup n/+1) is addressed in this paper. The unit realization adopts CMOS semi-custom VLSI design, using Octtools-5.0 with the standard cell MSU2-3 library. The implemented chip has the advantage of reduced delay time and hardware requirements. Thus, it can support real-time one and two dimensional signal processing applications. The design does not have dynamic range limitations due to the absence of memory, therefore, this implementation can be expanded for better reliability. Performance of the system is estimated to be 18 million residue arithmetic operations per second on 2 /spl mu/m process.