Design and optimization of a parallel architecture dedicated to image matching
Edwige E. Pissaloux, F. Le Coat, Patrick J. Bonnin, A. Tissot, F. Durbin · 1999
The design and optimised (in time and space) implementation of a systolic circuit dedicated to aerial image matching is proposed. The final run time data adaptive architecture evaluation with Xilinx XC 4010 XL offers the equivalent processing speed-up of 2000 (compared to a sequential solution).