A tool for two's complement, bit-level, fixed-point simulation of digital filters
Esam Abdel‐Raheem, F. El-Guibaly · 2002
A tool for software implementation of digital filter architectures is presented. The implementation is based on fixed-point arithmetic using bit-level logic modules to reflect the actual hardware. The tool can be used in academia as well as for hardware verification. Several finite-duration impulse response (FIR) and infinite duration impulse response (IIR) filter architectures are implemented to illustrate the capabilities of the tool.