Designing a Simple FPGA-Optimized RISC CPU and System-on-a-Chip
Jan Gray · 2000
Abstract This paper presents the complete design of a simple FPGA RISC processor core and system-on-a-chip in synthesizable Verilog. It defines a RISC instruction set architecture and then describes how to implement every part of the processor. Next, an interrupt facility is added. The second half of the paper describes the design and implementation of the system-on-a-chip on-chip RAM, peripheral bus, and peripherals. Throughout, FPGA-specific issues and optimizations are cited. The paper concludes with a comparison with other FPGA processor cores and a brief discussion of software tools issues. 1