A secure architecture for the design for testability structures
Samta D. Talatule, Pravin P. Zode, Pradnya Pravin Zode · 2015
Scan based Design for Testability structures are highly vulnerable to unauthorized access to the internal signals of a chip. This paper proposes a secure scan based design which prevents this unauthorized access without any compromise in the testability. The proposed secure architecture employs unique keys for each test vector. These unique keys are generated by a linear feedback shift register and are then embedded into the don't care bits of the test vectors. The bit size of the LFSR is kept higher than the key size in order to add another layer of security to the key. Since the keys are embedded into the test vectors itself, the area overhead is less. The level of security is increased significantly as not only the key changes for every test vector, but also its position in the test vector. The experimental results on the ISCAS'89 benchmark circuits show the effectiveness of the approach.