SOM on multi-FPGA ISA board-hardware aspects
Daisuke Suzuki, Omar Hammami · 2003
This paper describes the hardware design of a multi-FPGA hardware implementation of a 16 neurons Self-Organizing Map (SOM) artificial neural network. The SOM designed includes 16 neurons controlled in a SIMD execution mode. The application targeted is 3D to 2D projection. The clock frequency of the hardware design is 11.386 MHz and it has been implemented on 5 Xilinx FPGA chips mounted on a plug-an-play PC ISA board. The resulting hardware outperforms under some conditions several software simulations implementations running on various PC hardware.