Implementation of a programmable phased logic cell [FPGA]
Mutlu Aydin, Cherrice Traver · 2003
Traditional field programmable gate arrays (FPGAs) have been controlled by a global clock, which means that all signals have to be routed efficiently to meet the synchronous timing constraints. A phased logic FPGA does not require a global clock; it accomplishes its synchronization by encoding value and timing information of a single bit with two separate wires. In this project, two standard cell designs for a phased logic FPGA were simulated, fabricated in 0.5 /spl mu/m and 1.5 /spl mu/m CMOS technologies, and tested successfully.