A parallel generation system of compact IDDQ test sets for large combinational circuits
Tsuyoshi Shinogi, T. Hayashi · 2003
This paper presents a high performance compact IDDQ test generation system for detecting bringing faults, targeting large circuits. This system is based on the iterative-improvement-based method. We use a two-level parallel processing technique for speeding up the test generation significantly and invoke the assist of a deterministic ATPG for attaining 100% fault efficiency. The experimental results demonstrate its effectiveness.