Proteus-1: a general accelerator for CAD
Sean P. E. Smith, Benjamin P. Wood, James Little, Philip Hunter · Fall joint computer conference · 1987
The architecture of a low cost, highly flexible, general accelerator for Electronic Computer Aided Design (CAD) is presented. Previously reported special purpose compute engines for CAD addressed only one specific application (typically, logic simulation). In contrast, the Proteus-1, a dynamically reconfigurable multi-processor with both distributed and shared memory, significantly accelerates the low level operations fundamental to a variety of CAD applications. As a result of this approach, Proteus-1 maintains a high degree of flexibility while also achieving substantial performance gains over conventional mainframes. Logic simulation results are offered in support of these conclusions.