Functional VLSI design verification methodology for the CM-5 massively parallel supercomputer
M. St. Pierre, Shaw-Wen Yang, D.R. Cassiday · 2003
The methodology and techniques developed from the functional verification of five of the VLSI chips used in the CM-5, a massively parallel supercomputer, are described. The verification methodology uses multiple layers of abstraction and concurrent development of design and test to reduce overall development time and increase the effectiveness and coverage of the functional tests. Some of the pragmatic techniques proved useful include continuous monitoring of all interfaces and finite-state machines (FSMs), and demons to exercise the chip in difficult-to-reach states.>