Design of a CORDIC-based SIN/COS intellectual property (IP) using predictable sign bits
Tso-Pin Chuang, Chao-Chuan Huang, Shen‐Fu Hsiao · European Solid-State Circuits Conference · 2001
We propose an area-time efficient design for a redundant CORDIC-based SIN/COS generator by predicting the polarity of the micro-rotations using a novel technique called Base Angle Transformation. The proposed is designed and verified as a silicon intellectual property (IP). By predicting the polarity of the signed bit of the micro-rotation, the critical paths of the unfolded architectures involve only the X and Y recurrences. The implementations for 16-bit and 24-bit wide CORDIC-Based SIN/COS IP are synthesized using Xilinx FPGA tools with the area-time complexities presented. The proposed results save more than 30% hardware area with the speed-up of more than 25% compared with the exiting non-predictable methods. We also provide the simple and efficient verification strategy for this IP.