Algorithms and parallel VLSI architectures II : proceedings of the International Workshop, Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991
Parallel Vlsi Architectures, P. Quinton, Yves Robert · Elsevier eBooks · 1992
Parts: 1. Parallel Algorithms. Orthogonal lattice algorithms for adaptive filtering and beam forming (J.G. McWhirter, I.K. Proudler). Mapping QR decomposition of a banded matrix on a 1D systolic array with data contraflow and pipelined functional units (M. Valero-Garcia et al.). Algorithms and architectures for recursive total least squares estimation (M. Moonen). Meshes with flexible redundancy (R. Melhem, J. Ramirez). Systolic generation of derangements (S.G. Akl et al.). A 2D toroidal systolic array for the knapsack problem (R. Andonov, F. Gruau). A parallel program for the recognition of P-invariant segments (J. Katoen, B. Schoenmakers). Parallel algorithms for finding connected, independent and total domination in interval graphs (G.S. Adhar, S. Peng). Parallel algorithms for color image quantization on hypercubes and meshes (F. Dehne, A. Rau-Chaplin). A parallel thinning algorithm using the bounding boxes technique (S. Ubeda). Time-varying system theory for computational networks (A.J. van der Veen, P. Dewilde). 2. Synthesis Methodologies. Generalized cycle shrinking (W. Shang et al.). Direct mapping of nested loops on piecewise regular processor arrays (D.J. Soudris et al.). From systolic to periodic array design (V. Van Dongen). Linear systolic arrays for matrix multiplication: comparisons of existing synthesis methods and new results (T. Risset). Refinement based algorithm mapping techniques for linear systolic arrays (R. Varadarajan, B. Ravichandran). Specifying control signals for one-dimensional systolic arrays by uniform recurrence equations (J. Xue, C. Lengauer). An improved systolic algorithm for the algebraic path problem (S. Rajopadhye). Synthesis of size-optimal toroidal arrays for the algebraic path problem (P. Clauss et al.). A programmable VLSI array with constant I/O pins (M.A. Aboelaze et al.). Array design methodologies for real-time signal processing in the Cathedral IV synthesis environment (F. Catthoor et al.). Signal analysis and signal transformations for ASIC regular array architecture synthesis (M. Van Swaaij et al.). 3. VLSI Architectures. Experience in the design of parallel processor arrays (P. Frison, D. Lavenier). On the use of most significant digit first arithmetic in the design of high performance DSP chips (J. McCanny). On line computing: a survey and some new results (J.M. Muller). Delays of on-line floating point operators in borrow-save representation (J. Duprat et al.). Nonlinear adaptive filtering algorithms for parallel and systolic implementation (F. Rauf, H.M. Ahmed). Distributed simulation of parallel VLSI architectures (D.K. Arvind). Transe: an experimental design tool (G. Durrieu et al.). Matrix multiplication on an associative string processor: application to image compression by Gabor expansion (F. Dufaux, M. Kunt). Loop unrolling for processors with instruction cache (H.P. Charles). Implementing cellular automata on the ArMen machine (K. Bouazza et al.). 4.