The high-bandwidth 256kB 2nd-level cache on an itanium microprocessor
R. Riedlinger, T. Grutkowski · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2005
This paper describes the second level 256 kB unified cache incorporated into the next generation of the Itanium/spl trade/ processor family code named McKinley. The paper describes the datapath structures that provide a non-blocking, out-of-order interface to the processor core achieving a minimum 5-cycle latency with a standalone bandwidth of 72 GB/s.