Dynamic termination output driver for a 600 MHz microprocessor
S. Vishwanthaiah, M. Ang, Jonathan Starr, A. Taylor · 2002
Globally synchronous, multi-drop, bidirectional microprocessor system interfaces have the advantages of low latency and no synchronization penalty, and typically run at 100-120 MHz. Maximum operating frequency is limited by the time required for a signal transition initiated at the driving end to settle and reliably get sampled at the receiving end. Typical source-terminated systems (such as HSTL) require a round-trip transmission-line propagation delay to terminate the signal. With parallel terminated systems such as GTL with 2 nodes, a bus turnaround low-to-low switch with no dead-cycle needs a round-trip propagation delay to settle and be sampled reliably. The dynamic termination logic (DTL) system reduces the settling time to a one-way delay, by having the driver at the receiving end terminate the signal, and raises the signaling frequency to 150-200 MHz.