Virtual self-timed blocks for systems-on-chip
Yuan Chen, Fei Xia, Alex Yakovlev · 2006
Intellectual properties (IP cores) are widely used as pre-designed and reusable units in various system-on-chip (SOC) designs, but their integration has presented difficulties for system designers. In this paper, we propose an approach to better reuse IP cores while maintain energy efficiency for SOC systems. Here we employ a so called self-timed event processor (STEP) to make each IP core into a virtual self-timed block. Much of the IP cores' pre-designed properties can be preserved and the new SOC systems that use virtual self-timed blocks can be more energy efficient. A MATLAB based investigation is carried out on an example STEP processor.