A sea-of-gates FPGA
E. Goetting, D. Schultz, David B. Parlour, S.O. Frake, R. Carpenter, C. Abellera, B. Leone, D. Marquez, M. Palczewski, E.E. Wolsheimer, Michael J. Hart, K. Look, Martin L. Voogel, G. West, V. Tong, Andrew Chang, Daewon Chung, Wen-Yuan Hsieh, L. Farrell, W. Carter · 2002
This CMOS FPGA has programmable interconnect vertically stacked above the logic cells, allowing 2-fold reduction in silicon area while maintaining mutability. This FPGA logic architecture is designed to efficiently implement HDL code, an increasingly important attribute as synthesis tools become prevalent in design entry. To derive an equivalent sea-of-gates gate array (SOG-GA) capacity for the device, parallel-synthesis is employed, with HDL designs synthesized in both the FPGA and gate array.