A hardware implementation in FPGA of the Rijndael algorithm
C. Chitu, D. Chien, Chih Feng Chien, Ingrid M.R. Verbauwhede, Fu-Yu Chang · 2003
Implementation in FPGA of the new Advanced Encryption Standard, Rijndael, was developed and experimentally tested using the Insight Development Kit board, based on Xilinx Virtex II XC2V1000-4 device. The experimental clock frequency was equal to 75 MHz and translates to the throughputs of 739 Mbit/s for Rijndael with block size and key size of 128 bits, respectively. This circuit has capability to handle encryption/decryption and fitted in one FPGA taking approximately 84% of the area. Our work supplements and extends other research efforts.