A 3D Data Transformation Processor
Dimitrios Megas, Timothy E. Levin, Ted Huffmire, Kleber Pizolato · 2012
Application-specific coprocessors, including those for cryptography and compression, can provide significant acceleration and power savings to programs requiring their services. While most coprocessors have traditionally been constructed as a separate chip connected to the main CPU over a relatively slow bus connection, 3D integration, providing a more direct connection, is an emerging technology that offers significant performance advantages and power savings over such systems. With 3D integration, two or more dies can be fabricated separately and later combined into a 3D integrated circuit (3D IC), a single stack of two or more dies connected by vertical conductive posts. We propose a novel coprocessor architecture in which one layer houses application-specific coprocessors for cryptography and compression, which provide acceleration for applications running on a general-purpose processor in another layer. A compelling application for such a system is one that performs real-time trace collection, compressing the trace prior to its transmission to permanent off-chip storage for offline program analysis. Furthermore, an optional encryption step, performed by the cryptographic circuitry in the coprocessor layer, can protect this compressed data from interception. In another application, a high-performance stand-alone encryption service can be provided.