A 900 MHz 2.25 MB cache with on-chip CPU now in Cu SOI
J. M. Hill, J. Lachman · 2002
The 500 MHz 1.5 MB cache with 50% increased bit count described is ported from a 0.25 /spl mu/m bulk technology to a 0.18 /spl mu/m SOI process with local interconnect. The SOI technology used presented significant design challenges to match the 80% frequency increase expected for the CPU.