A parallel architecture for estimating 4th-order cumulants
Johnny Lim, Cheng‐Chew Lim · 2002
A novel parallel architecture for estimating computationally intensive 4th-order cumulants is presented. Different from most systolic array implementations, a MIMD array processor is used to efficiently compute the cumulants by exploiting the algorithmic parallelism, reducing operand-fetching operations and by optimising the processing elements' architectural design. It is shown that by breaking the algorithm into a number of separate stages and reorganising all computations in matrix block form, a significant computational speed-up can be obtained, which increases the applicability of cumulant-based algorithms in a real-time system.