Parallel Combinator Reduction: Some Performance Bounds
Mike S. Joy, Tom Axford · Warwick Research Archive Portal (University of Warwick) · 1992
A parallel graph reduction machine simulator is described. This performs combinator reduction and can simulate various different parallel reduction strategies. A number of functional programs are examined, and experimental results presented comparing the amount of parallelism obtainable using explicit divide-and-conquer with the maximum amount of parallelism available in the programs.