Design and Evaluation of a Distributed Cache Architecture with Prediction
Thomas M. Alexander, Gershon Kedem · 1994
We propose a secondary cache architecture that combines a predictive fetch strategy with a distributed cache to build a high performance memory system. The cache is partitioned into smaller units and distributed evenly in the main memory space. The architecture o#ers high bandwidth between the cache and the DRAM memory. A hardware prediction scheme is used to prefetch data into the cache and hide the high DRAM latency. The prediction scheme does not rely on any predetermined data access patterns and is completely transparent to the user. Simulation of our architecture on a set of benchmark programs showed a 40%-90% improvement in the e#ective memory access time when compared to traditional caching. 1 Introduction An increasing number of high-end workstations are being used as compute servers to solve large scientific problems. Present day microprocessors can compute at a very high speed. However, main memory access time did not keep pace with the improvements in the process...