An efficient and customized pipelined cryptography hardware
Otávio de Souza Martins Gomes, Robson Luiz Moreno, Tales Cleber Pimenta · International Conference on Ultra Modern Telecommunications · 2011
This article describes the core implementation of an Advanced Encryption Standard — AES in Field Programmable Gate Array — FPGA. The core was implemented in both Xilinx Spartan-3 and Xilinx Virtex-5 FPGAs. The algorithm was implemented for 128 bits word and key. The implementation was very efficient, achieving 318MHz on a Xilinx Spartan-3, representing at 50% faster than other reported works. The implementation can achieve 800MHz on a Xilinx Virtex-5. The main goal of this work was the implementation of a fast and modular AES algorithm, as it can be easily reconfigured to 128, 196 or 256 bits key, and can find a wide range of applications. Nevertheless, all the reported works used as comparison basis to our work were also implemented using 128 bits key. A pipelined hardware was implemented and it was compared with non-pipelined version, as a result was achieved an increase in the efficiency.