OpenMP for Chip Multiprocessors
Feng Liu, Vipin Chaudhary · 2005
This chapter contains sections titled: Introduction 3SOC Architecture Overview Quads Communication and Synchronization Software Architecture and Tools The OpenMp Compiler/Translator Data Distribution Computation Division Communication Generation Extensions to OpenMP for DES Controlling the DSEs Extensions for DSEs Optimization for OpenMP Using MTE Transfer Engine Double Buffer and Data Prefetching Data Privatization and Others Implementation Performance Evaluation Conclusions Reference The emergence of System-on-Chip (SOC) design shows the growing popularity of the integration of multiple-processors into one chip. In this paper, we propose that high-level abstraction of parallel programming like OpenMP is suitable for chip multiprocessors. For SOCs, the heterogeneity exists within one chip such that it may have different types of multiprocessors, e.g. RISC-like processors or DSP-like processors. Incorporating different processors into OpenMP is challenging. We present our solutions to extend OpenMP directives to tackle this heterogeneity. Several optimization techniques are proposed to utilize advanced architecture features of our target SOC, the Software Scalable System on Chip (3SoC). Preliminary performance evaluation shows scalable speedup using different types of processors and performance improvement through individual optimization.