Synthesizing VHDL from Activity Models in UML 2
Tomás Balderas-Contreras, René Cumplido, Gustavo Rodríguez · International Journal of Circuit Theory and Applications · 2012
ABSTRACT This document describes a synthesis technology that generates structural VHDL code from models describing the flow of data required to perform algorithms operating on bit‐blocks. The models are built using restricted activity diagrams in the Unified Modeling Language version 2. The code generator is developed using Acceleo, a technology to implement transformations from models to text. The technology described in this paper exploits the principles of object orientation and model‐driven engineering. The primary aim is to improve productivity and alleviate complexity during the design of digital hardware systems that implement demanding operations used by a wide variety of computing devices. The use of the technology is illustrated with the generation of VHDL code from models describing a block cipher algorithm. Copyright © 2012 John Wiley & Sons, Ltd.