A pipelined 32b microprocessor with 13Kb of cache memory
Alan D. Berenbaum, Brian W. Colbry, David R. Ditzel, R.D. Freeman, Hubert R. McLellan, M. Shoji, Kevin R. O'Connor · 1987
A Reduced Instruction Set Computer containing 172K transistors in 1.5μm technology will be described. The chip contains caches for prefetch buffer, decoded instructions and stack. Two internal machines with three pipelined stages are used.