Framework of timed trace theoretic verification revisited
Bin Zhou, Tomohiro Yoneda, C. Myers · 2002
For the formal verification of asynchronous circuits, a framework to support trace theoretic verification of timed circuits and systems was developed. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.