Code generation tools for hardware implementation of FEC circuits
C. Schuler · 2003
During the last decade the use of hardware description languages (HDL) became an important method for the specification and the design of VLSI circuits. In particular the combination with logic synthesis tools allows a significant acceleration of the design cycle. Further advantages are the use of top down design methodology, reuse of code and retargeting to different semiconductor technologies. Nevertheless there is a lot of effort spent in developing tools and languages, which allow a higher level of abstraction and by this a further improvement of the design efficiency. This paper focuses on application specific code generation tools, which might be used in many areas of digital hardware design. The concept is validated on the example of parameterized Forward Error Correction (FEC) circuits, which are used for error detection or correction in most communication systems. The code generators are able to generate the synthesizable VHDL (Very High Speed Integrated Circuits Hardware Description Language) description of complete FEC encoders and decoders within less than a second.