An improved algorithm for high-speed floating-point addition
Nhon Quach, Michael J. Flynn · 1990
This paper describes an improved, IEEE conforming floating-point addition algorithm. This algorithm has only one addition step involving the significand in the worst-case path, hence offering a considerable speed advantage over the existing algorithms, which typically require two to three addition steps. Key Words and Phrases: Improved floating-point addition algorithm, floating-point hardware design, IEEE rounding Copyright c fl 1996 by Nhon T. Quach and Michael J. Flynn Contents 1 Introduction 1 2 A Brief Review of FP Addition Algorithm 1 3 The New Algorithm 3 3.1 General Ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.2 Logic Equation for C in for the RTN Mode: . . . . . . . . . . . . . . . . . . 4 3.2.1 General Equation for C in : . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2.2 Applying C in to the Three Cases . . . . . . . . . . . . . . . . . . . . 5 3.2.3 Merging Case 1 and Case 2 . . . . . . . . . . . . . . . . . . . . . . . 11 4 Sum...