On mapping a multi-target tracking algorithm onto parallel processing architectures
Krishna Rao Pattipati, R. Lee, T. Kurien, Peter B. Luh · 2005
This paper is concerned with the mapping of application algorithms onto parallel computing architectures. The algorithm is characterized by a finite, directed, acyclic task graph representing the logical and data dependencies among the tasks constituting the algorithm, while the parallel computer is represented by a finite, undirected processor graph. The mapping problem is viewed as one of assigning the nodes of the task graph onto the nodes of the processor graph such that the completion time of the algorithm is minimized (or equivalently speedup is maximized). The mapping problem is NP-hard and as a result all practical mapping methods incorporate heuristics. We develop a two-stage heuristic mapping algorithm, which has been proven to be optimal for series-parallel task graphs as the number of tasks in the parallel portions of the task graph tends to infinity and when the communication times are neglected. The mapping algorithm is applied to study the effects of granularity and processor architectures on the speedup of a multi-target tracking algorithm. From the simulation results, it is concluded that the task granularity is a a major determinant of speedup, and that speedup can be further improved if clustering and global hypothesis formation stages of the tracking algorithm can be parallelized.