A 600MIPS 120mw 70μA leakage triple-CPU mobile application processor chip
S. Torii, Saya Suzuki, H. Tomonaga, Tatsuya Tokue, Junji Sakai, N. Suzuki, Koso Murakami, Takefumi Hiraga, Koji Shigemoto, Y. Tatebe, Eisaku Ohbuchi, Norio Kayama, Masato Edahiro, T. Kusano, N. Nishi · 2005
A triple-CPU mobile application processor is developed on an 8.95mm/spl times/8.95mm die in a 0.13/spl mu/m CMOS process. The IC integrates 3/spl times/ARM926 cores, a DSP several accelerators, as well as strong bus and memory interfaces. It consumes 120mW for digital TV, Web browser, and 30 graphics, and 250mW@200MHz for 600MIPS with full processing.