A realtime microprogrammable video signal LSI
M. Yamashina, Tadayoshi Enomoto, T. Kunio, Ichiro Tamitani, Hidenobu Harasaki, T. Nishitani, Mitsuya Sato, Koichi Kikuchi · 1987
A signal processor employing a 3-stage pipelined architecture for efficient realtime video operations, such as edge filtering, motion picture coding and motion compensation, will be reported. Chip incorporates a peak value detector allowing high-speed vector quantization and pattern matching operation. The chip (94.5mm2) uses a 2.5μ CMOS double layer metal process and operates at 14.3MHz.