A 0.6 μm BiCMOS processor with dynamic execution
Robert P. Colwell, R. Steck · 2002
A next generation, Intel-Architecture compatible microproceesor with dynamic execution is implemented in 0.60 /spl mu/m 4-layer metal BiCMOS. Performance is achieved through the use of a large, full-speed cache accessed throrgh a dedicated bus interface feeding a generalized dynamic execution microengine. A primary 64 b processor bus includes additional pipelining features to provide high throughput to this CPU and cache. These and other techniques result in a projected performance of >200 Ispec92. Testability features built into the design allow complete access to all structures without the overhead of a full LSSD implementation. This processor implements dynamic execution using an out-of-order, speculative-execution engine, with register renaming of integer floating-point and flags variables, multiprocessing bus support, and carefully-controlled memory access reordering.